Renesas

Description

DATASHEET PE. TE. 9. 2. 1. 7. 10. 3. 4. 5. 6. 14. 13. 12. 11. 15. Q0. Q1. Q2. Q3. TC. P0. P1. P2. P3. CD54/ 74HC161 , CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Nov 19, 2001 from 5V. If you require 3V operation, substitute a MAX7405 for the filter and (if operating beyond the 74HC161 voltage or frequency range) a combination of the CS signal and the 74HC161 counter so that for each CS signal the clock circuit generates 12 pulses and then is gated off. These 12 pulses 74HC161 . CLEAR. 1. CLK. 2. P0. 3. P1. 4. P2. 5. P3. 6. PE. 7. GND. 8. LOAD. 9. TE. 10. Q3. 11. Q2. 12. Q1. 13. Q0. 14. Tc. 15. VCC. 16. CNT2. 74HC161 . presettable synchronous BCD decade counter; asynchronous reset;. TTL- enabled. . . 74HC161 . Binary counters/ timers presettable synchronous 4-bit binary.