Description
Aug 12, 2016 RL78 CPU Core. CISC architecture with 3-stage pipeline. Minimum instruction execution time: Can be changed from high speed (0.03125 Oct 6, 2014 Revision History. Revision history of RL78/G14 restrictions. Document Number. Date issued. Description. TN-RL*-A025A/E. April 9, 2014.
Part Number | R5F104LFDFB |
Brand | Renesas |
Image |
R5F104LFDFB
RENRSAS
5000
0.27
S.E. Components
R5F104LFDFB
rene
10000
0.89
Win-Win Electronic Technology Limited
R5F104ADASP#V0
ren
50
1.51
Pacific Corporation
R5F104AADSP
RENESA
1882
2.13
Yingxinyuan INT'L (Group) Limited
R5F104AADSP
RENESAS/NEC
1365
2.75
HK TWO L ELECTRONIC LIMITED